1. Field of the Invention
The present invention relates to dynamic random access memory (DRAM). Moreover, the present invention relates to DRAM fabricated by slightly modifying a conventional one-transistor static random access memory (1T-SRAM-Q) process, which in turn is a slight modification of a conventional logic process.
2. Related Art
FIG. 1 shows a schematic of a conventional DRAM cell 1 that is fabricated using a conventional logic process. As used herein, a conventional logic process is defined as a semiconductor fabrication process that uses only one layer of polysilicon and provides for either a single-well or twin-well structure. DRAM cell 1 consists of p-channel MOS access transistor 2 (referred to here as pass gate), p-channel MOS transistor 3, word line electrode 4 (which is coupled to the gate terminal of access transistor 2), and bit line electrode 5 (which is coupled to the drain terminal of access transistor 2). P-channel transistor 3 is configured to operate as a charge-storage capacitor, with the source and drain of this transistor 3 being commonly connected. P-channel transistor 3 is hereinafter referred to as a cell capacitor.
FIGS. 2A-2D are cross sectional views illustrating an embedded DRAM process flow resulting in the manufacture of an array of DRAM cells (identical to DRAM cell 1) in memory array region 10 and conventional logic devices in logic region 11. As shown in FIGS. 2A-2D, the array of DRAM cells are fabricated side-by-side on the same chip with conventional logic devices.
As shown in FIG. 2A, a mask layer 1200 is formed over p-type substrate 1000. A photoresist mask 1300 is formed over mask layer 1200 as illustrated. The openings in photoresist mask 1300 define the locations of subsequently formed shallow trench isolation (STI) structures.
As shown in FIG. 2B, an etch is performed through photoresist mask 1300, thereby removing the exposed portions of mask layer 1200. Photoresist mask 1300 is stripped, and a shallow trench etch is then performed to a depth DSTI through the patterned mask layer 1200.
As shown in FIG. 2C, patterned mask layer 1200 is removed, n-type well region 1100 is formed, the trenches formed in FIG. 2B are filled with a STI dielectric 120, such as SiO2. STI dielectric 120, which has a depth DSTI, is used to isolate active circuitry, including logic gates and memory cells. Another patterned mask layer 1320 is formed over the resulting structure. Patterned mask layer 1320 includes an opening, which exposes a portion of n-well region 1100 and STI dielectric 120 as illustrated. An etch is performed through this opening, thereby removing a portion of the exposed STI dielectric 120, and exposing a sidewall section of the trench. As described below, this etch allows the formation of a folded capacitor structure. This folded capacitor structure saves cell area while still maintaining large capacitance, thereby allowing the resulting DRAM memory cell to operate properly. STI dielectric 120 maintains a thickness T1 at the bottom of the trench. The remaining thickness T1 of the recessed STI region is thick enough to prevent formation of an inversion layer directly under the recessed region, thereby isolating memory cells adjacent to the recessed STI dielectric 120.
A P− type implant is performed through the opening of patterned mask layer 1320, thereby forming P− doped layer 140 in well region 1100. Note that N-well 1100 isolates the array memory cells from other circuits on the die and from the large body of substrate 1000, therefore improving noise immunity and soft-error-rate of the memory.
As shown in FIG. 2D, patterned mask layer 1320 is removed, and processing continues with the formation of gate dielectric layers 130-131, conductive elements 101, 100A, 100B and 100C (with adjacent sidewall spacers), P− regions 150, 160 and 161, P+ regions 170-171, metal salicide regions 180-181, and salicide blocking layer 190. In one embodiment, conductive elements 101, 100A, 100B and 100C are formed over gate dielectric 130-131 using the conventional logic process polysilicon layer. Salicide regions 180-181 are simultaneously formed in both memory and logic areas, thereby forming high-performance transistors. It is desirable to exclude salicide from the charge storage regions 150 and 140; therefore, salicide blocking layer 190 is used to prevent salicide formation in these regions. Logic devices formed in area 11 also contain conventional logic LDD and source/drain diffusions 161 and 171, respectively.
Conductive element 100A forms a gate electrode of a p-channel transistor corresponding with access transistor 2 (FIG. 1). Gate dielectric 130, salicide layer 180, P+ diffusion region 170 and P− diffusion regions 150 and 160 form the remaining elements of this access transistor. Salicide layer 180 and P+ diffusion region 170 provide reduced contact resistance for an associated bit line (not shown). P− type layer 140 and conductive element 100B are separated by gate dielectric 130, thereby forming a capacitor corresponding with cell capacitor 3 (FIG. 1). P− diffusion region 150 couples the access transistor to MOS capacitor 3. The cell capacitor stores charge in an inversion layer in the substrate located under conductive element 100B. This inversion layer is formed by applying a large negative voltage to capacitor gate 100B.
Although FIG. 2D only illustrates PMOS logic devices, it is understood that NMOS logic devices outside of N-well 1100 are also part of the integrated circuit.
The fabrication process of FIGS. 2A-2D is described in more detail in connection with FIGS. 3G-3S of U.S. Pat. Nos. 6,642,098 and 6,573,548. Hereafter, this fabrication process is referred to as the “1T-SRAM-Q process”.
The conventional 1T-SRAM-Q memory process shown in FIGS. 2A-2D has one major shortcoming. Namely, as the technology scales in sub-90 nm dimensions, the STI thickness (DSTI) gradually decreases. At the same time, the thickness T1 cannot arbitrarily decrease because this thickness is required to prevent cross-cell leakage within the process variation of memory cell parameters. It is therefore challenging to maintain acceptable cell capacitance, which enables proper DRAM memory read operations, as technology scales.
It would therefore be desirable to have an embedded DRAM process, which resolves the above-described capacitance scaling limitation.